IEEE

High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC

Abstract: Recent advances in hardware acceleration for postquantum cryptography (PQC) have also switched to lightweight PQC. Apart from the traditional hardware design methodology, instruction-set ...
IEEE

A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations

Abstract: Deep neural network (DNN) inference relies increasingly on specialized hardware for high computational efficiency. This work introduces a field-programmable gate array (FPGA)-based ...