While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...

SAN MATEO, Calif. — To achieve first-pass timing closure on complex ASICs, designers must ensure their chip architecture design and RTL design are physical synthesis-friendly. That was the bottom-line ...

Traditionally, formal verification is used after the fact for bug hunting or design-rule checking. It has yet to be applied up front, where it would affect design decisions at the RTL coding stage.